This invention relates to a substrate attracting and holding system for grasping a substrate or workpiece and, more particularly, to a substrate attracting and holding system for use in a semiconductor manufacturing apparatus, a liquid crystal substrate manufacturing apparatus, a magnetic head manufacturing apparatus, a semiconductor inspection apparatus, a liquid crystal inspection apparatus, or a magnetic head inspection apparatus or for use in manufacture of a micro-machine, for example. In another aspect, the invention concerns an exposure apparatus or a device manufacturing method using such a substrate attracting and holding system.
In reduction projection exposure apparatuses used in the manufacture of semiconductor devices, for example, enlargement of the numerical aperture (NA) has been promoted to meet miniaturization of a device (chip). Although the resolution is improved by a larger numerical aperture, the effective depth of focus is shortened on the other hand. Thus, in order to maintain the resolution while keeping a sufficient practical depth, attempts have been made reduce the curvature of image field of a projection optical system or to improve the wafer flatness in regard to wafer thickness non-uniformness or flatness precision of a chuck.
One factor for causing degradation of the flatness of a wafer surface is the presence of a foreign particle caught between a chuck and a wafer. If a foreign particle of a few microns is once caught therebetween, the wafer at that portion is deformed and raised thereby. Where the effective depth of focus is 1 micron or less, local defocus occurs there and, in a worst case, a pattern defect is produced. In order to avoid degradation of the product yield rate due to such foreign particles, based on the probability, pin contact chucks (pin chucks) wherein the contact rate between a chuck and a wafer is reduced to a minimum are used prevalently.
As regards a machine for processing a substrate such as a semiconductor wafer, for semiconductor device manufacture, or a liquid crystal substrate, for liquid crystal display device manufacture, for example, a projection exposure apparatus, generally it uses a substrate attracting and holding system based on a vacuum attraction force to hold and secure a substrate (workpiece) and to correct any warp thereof to keep its flatness. FIG. 31 shows an example of such substrate attracting and holding system. In the substrate attracting and holding system (chuck) 201 illustrated, a substrate carrying plane is defined by a carrying table which comprises a plurality of pin contact type protrusions 202 disposed in a grid and a peripheral rim type protrusion 203 provided at the peripheral portion of the carrying plane for supporting the peripheral portion of a substrate. Also, there are suction holes 205 formed at the carrying plane where the contact type protrusions are provided, which holes are communicated with a vacuum piping system for reducing the pressure between the carrying plane and a substrate to be carried thereon.
The substrate attracting and holding system of a structure such as described above is used in a semiconductor exposure apparatus, for example. A wafer which is a substrate is conveyed onto the chuck 201 by means of a conveying system. After the wafer is placed on the chuck 201, it is held fixed on the chuck 201 by vacuum attraction applied through the attraction holes 205. Here, in order to reduce the probability of occurrence of deformation of the wafer surface due to catching a foreign particle between the chuck carrying table and the wafer, the total area of the substrate supporting protrusions distributed along the carrying plane is made small.
In the substrate attracting and holding system such as described above, the layout of the substrate supporting protrusions which provide the chuck carrying table is determined without any specific concern to the processing region on the substrate. It is set without any positional relationship with the substrate processing region. Namely, if the substrate processing region changes, the same chuck is used continuously. Therefore, if the surface of a substrate is deformed as a result of the attraction and holding of the substrate, the deformation may cause not only a deformation of that portion of the substrate in a vertical direction but also a distortion along the plane of the substrate. Further, the layout of the substrate supporting protrusions of the chuck is determined without any specific concern to the layout of alignment marks of a substrate. If the alignment mark layout of the substrate changes, the same chuck is used continuously. While a deformation of the substrate surface resulting from the attraction and holding of the substrate may cause an error in the coordinate of an alignment mark, since the relationship between each substrate alignment marks and each substrate supporting protrusions of the chuck is unknown, it is not possible to correct the coordinate error and, therefore, the registration precision is degraded.
On the other hand, in a lithographic process among semiconductor manufacturing processes in which a very fine pattern is transferred by exposure, in consideration of the depth of focus being decreased with miniaturization of the device or a coordinate error of a pattern to be transferred, the flatness of a substrate as held by a chuck has to be decreased as much as possible. If the substrate has a distortion along a horizontal direction caused by the deformation of the substrate surface, the error in the coordinate of an alignment mark of the substrate becomes large as a result of it. Additionally, if such coordinate error is different in each region (hereinafter, xe2x80x9cshotxe2x80x9d) to be processed by a single operation or in each semiconductor device (hereinafter, xe2x80x9cdiexe2x80x9d), since a semiconductor device is produced by superposing various patterns, the pattern registration is much degraded. If there is a large difference between shots, it can not be corrected easily and, in a worst case, a defect of a semiconductor device is produced.
It is known that, in a pin chuck, a wafer is deformed and warped between pins of the chuck due to vacuum attraction and that this causes degradation of the flatness of the wafer surface. Many proposals have been made to solve this problem. For example, Japanese Patent No. 2574818 proposes a structure wherein a ring-like groove is formed in an outer peripheral portion of a chuck and wherein pins are provided in a central portion, inside the groove, at a pin pitch of 2 mm or less, so as to keep good wafer flatness at the chuck peripheral portion and good wafer flatness within the pin pitch at the chuck central portion. In this patent, it is stated that, with a pin chuck having pins disposed in a grid, the flatness within the pin pitch can be approximated by a model of a beam having both ends free-supported and that, from a desired flatness, a required pin pitch can be made 2 mm or less. However, the approximation with the beam having both ends free-supported means that the pin pitch as a whole is determined by using the condition for the support with the free end at the outer peripheral portion which condition is worse than that at the central portion. There is no disclosure about determining optimum pin pitches for the flatness at the outer peripheral portion and at the central portion, respectively. Therefore, this causes an inconvenience that the pin pitch at the central portion becomes smaller than as required and, as a result, the contact rate becomes larger than as required.
In an attempt to solving this problem, Japanese Patent No. 2821678 proposes a structure wherein the pin pitch at a central portion of a chuck is made larger than that at an outer peripheral portion of the chuck, thereby to improve the wafer flatness at the chuck outer peripheral portion and the chuck central portion while keeping the contact rate small. According to this proposal, it is suggested that the flatness within the pin pitch at the peripheral portion can be approximated with a model of a beam having one end fixed and another end free-supported, while the flatness within the pin pitch at the central portion can be approximated with a model of a beam having both ends fixed, and that the ratio between the pin pitches at the peripheral portion and the central portion can be optimized.
In the proposal made in Japanese Patent No. 2821678, however, there is an assumption that the attraction force is even at the outer peripheral portion of the chuck and at the central portion of it. There is no disclosure about determining optimum attraction forces for the wafer flatness at the chuck outer peripheral portion and the chuck central portion, respectively. Also, there is no disclosure about determining an optimum relationship between the pin pitch and the attraction force, for the wafer flatness.
Although such wafer flatness, that is, degradation of the wafer surface flatness due to a warp produced within the pin pitch, is in fact a problem to be solved, there is a much more serious problem that a distortion (wafer distortion) is in practice produced due to the warp within the pin pitch. For example, where a wafer of a 200 mm diameter being currently widely used is placed on and attracted to a pin chuck having pins arrayed in a grid with a pin pitch 2 mm, there may occur a wafer distortion of about 1/2.6 of the wafer flatness. In a semiconductor process of 0.25 micron rule, being mass-produced currently, the tolerance for the wafer flatness is 80 nm if it is set to be 10% of a depth of focus 800 nm, whereas the tolerance for the wafer distortion is 5 nm if it is set to be 10% of an overlay precision 50 nm. This value when converted into a wafer flatness becomes equal to 13 nm which is much smaller than 80 nm. Namely, it is seen that, as compared with the flatness as required by the depth of focus, the flatness as required by the overlay precision is much more strict. Conventionally, the flatness correction has been made so as to reduce the wafer flatness to a tolerance, whereas it has never been done so as to reduce the wafer distortion to a tolerance. As a result, the wafer distortion may be more than the tolerance, causing a degraded overlay precision and a decreased yield rate. Alternatively, an additional process margin may be needed, which may obstruct further miniaturization of a semiconductor device or further enlargement of integration of it.
In the aforementioned Japanese Patent No. 2821678, it is stated that, when the flatness at the outer peripheral portion of a wafer is made better, a positional deviation of an alignment mark at the wafer peripheral portion can be reduced like a positional deviation of an alignment mark at the wafer central portion. However, there is no quantitative statement about the alignment mark positional deviation. Further, there is no recognition of the inconvenience of a wafer distortion resulting from a warp within the pin pitch at the chuck central portion. There is no disclosure about determining an optimum relationship between the pin pitch and the attraction force, in respect to the wafer distortion. There is no disclosure about determining the relationship with respect to each of the peripheral portion and the central portion, respectively. Namely, there is no disclosure of reducing the wafer distortion to a tolerance.
It is accordingly an object of the present invention to provide a substrate attracting and holding method, a substrate attracting and holding system, an exposure apparatus and/or a device manufacturing method using a substrate attracting and holding system, by which the influence, upon a substrate processing precision, of an error in coordinate of an alignment mark to be produced by deformation of the surface of the substrate resulting from the attraction and holding of the substrate.
In accordance with an aspect of the present invention, there is provided a substrate attracting and holding system, comprising: a holding table for holding a substrate; a protrusion provided on said holding table, said protrusion being disposed to be placed in a predetermined positional relationship with a position of an alignment mark to be used for processing the substrate or a position with respect to which an alignment mark is to be produced.
It is another object of the present invention to provide a substrate attracting and holding system, an exposure apparatus and/or a device manufacturing method using a substrate attracting and holding system, by which a distortion or degradation of a flatness of the surface of a substrate such as a wafer, for example, due to a deformation of the substrate surface to be produced when the substrate is attracted and held by using a plurality of protrusions, can be reduced so that the substrate can be attracted and held in an optimum state and that an overlay precision can be improved.
In accordance with another aspect of the present invention, there is provided a substrate attracting and holding system having a plurality of protrusions for supporting a substrate, for attracting and holding the substrate supported on the protrusions, characterized in that a disposition pitch L of the protrusions and an attraction force P of the substrate are set so as to satisfy a relation:
Pxc2x7L3xe2x89xa6[36xc2x7Exc2x7h2xc2x7dxdy]/[{square root over (3)}xc2x7kxc2x7c]
where dxdy is a distortion tolerance, E is a longitudinal elasticity coefficient, h is a thickness of the substrate, c is a correction coefficient based on the protrusion disposition and k is a neutral plane correction coefficient.
These and other objects, features and advantages of the present invention will become more apparent upon a consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.